Imec Announces Sub-1nm Transistor Roadmap, 3D Stacked CMOS 2.0 Plans

Imec Announces Sub-1nm Transistor Roadmap, 3D Stacked CMOS 2.0 Plans

Imec, the world’s most superior semiconductor analysis agency, not too long ago shared its sub-1nm silicon and transistor roadmap on the ITF World occasion held in Antwerp, Belgium. The roadmap offers us an concept of ​​the timelines to 2036 for the following main processing nodes and transistor architectures that the corporate will analysis and develop in its labs in collaboration with business giants corresponding to TSMC, Intel, Samsung and ASML. The corporate has additionally outlined the transition to what it calls CMOS 2.0, which can contain separating a chip’s useful models, corresponding to L1 and L2 caches, from in the present day’s chip-based approaches to extra superior 3D designs.

As a reminder, ten Angstroms equal 1nm, so Imec’s roadmap covers course of nodes beneath ‘1nm’. The roadmap outlines that customary FinFET transistors will last as long as 3nm, however will then transfer on to new Gate All Round (GAA) nanolayer designs that can enter high-volume manufacturing in 2024. Groundbreaking designs corresponding to CFETs and atomic channels at A5 and A2, respectively, adopted.


(Picture credit score: imec)

Migrating to those smaller nodes is getting dearer over time, and the usual strategy to creating monolithic chips with a single giant die has lengthy since been changed by chips. Chip-based designs divide the assorted chip capabilities into totally different interconnected dies, permitting the chip to perform as a single cohesive unit, albeit with trade-offs.

Imec’s imaginative and prescient for the CMOS 2.0 paradigm consists of breaking apart chips into even smaller items by dividing caches and reminiscence into their very own models with totally different transistors, after which stacking different chip capabilities in a 3D association. This technique can even rely closely on rear facet energy distribution networks (BPDN), which route all energy from the again facet of the transistor.

Let’s take a more in-depth take a look at the imec roadmap and the brand new CMOS 2.0 methodology.

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