Intel 14th Gen Meteor Lake CPUs May Include L4 Cache
It is no secret that Intel is making ready the 14th Gen Meteor Lake to rival the perfect CPUs. The chipmaker has already shared some function units for the upcoming Foveros packaged chips. Nonetheless, a brand new Linux patch It implies that Meteor Lake will use a hardly ever used L4 cache on processors.
from the assertion Linux patch it reads: “In MTL, GT can not allocate LLC – solely the CPU can allocate. This requires a MOCS/PAT desk replace with the addition of ADM/L4 cache help.”
Yama didn’t specify what “ADM” means. Could be a flowery advertising and marketing identify for the L4 cache. The code did not present the scale of the ADM both. Traditionally, Intel has used 64MB for eDRAM or 128MB for Haswell by way of Espresso Lake. Throughout the Scorching Chips 34 presentation, Intel shared schematics of the Meteor Lake chip, which consists of 4 completely different tiles: CPU tile, SoC tile, IO expander tile, and graphics tile. The quad sits on a big base tile that acts as an middleman.
Intel’s first utility of eDRAM (embedded DRAM) was with Haswell, and it served as an L4 cache for the CPU and iGPU. It will proceed this follow till the chipmaker Espresso Lake. Nonetheless, solely a choose few desktop and cellular chips benefited from eDRAM throughout its brief lifetime. Broadwell was an important structure able to eDRAM. Chip producers usually exclude L4 cache from their designs as it’s slower.
The cache hierarchy runs from L1 to L4, however most processors cease at L3 as a result of pace drops as you go down the rungs. Decrease degree caches are bigger and subsequently enhance the possibility of cache hits. The primary drawback is that it takes longer to entry decrease caches like L3 and even L4. So, apart from feeding the built-in graphics, there are only a few situations the place L4 cache helps system efficiency. Nonetheless, in response to some Linux patches Coelacanth’s Dream revealed, L4 cache could make a comeback with Meteor Lake.
The actual query is the place Intel will place the ADM/L4 cache. Meteor Lake’s base tile could home the L4 cache. For instance, Ponte Vecchio’s base tile carries 144MB of L2 cache, so this has precedent. Alternatively, the L4 cache may be discovered contained in the SoC tile and will actually clarify its expansive panorama.
One other thrilling discovery is that Intel apparently blocked Meteor Lake’s iGPU from accessing LLC (end-level cache). In keeping with developer notes Linux patch (opens in new tab)“In MTL, GT is not allotted to LLC, set has_llc=0.”
LLC corresponds to the very best numbered cache on the processor that should hit reminiscence. L3 is often LLC in most trendy processors, shared between the CPU cores and the iGPU. For instance, Intel’s present thirteenth Gen Raptor Lake chips include as much as 36MB of L3 cache, which represents a 20% enchancment during the last twelfth Gen Alder Lake components. Nonetheless, the Linux patch states that solely CPU cores in Meteor Lake can enter LLC. The design is just like AMD’s Ryzen APUs the place the CPU cores and iGPU don’t share the identical cache.
The 12-core Meteor Lake processor just lately surfaced on a benchmarking website. Sadly, the chip’s misreported clock speeds and outcomes can’t present a concrete image of how a lot efficiency acquire we are able to count on in Raptor Lake. Due to this fact, it’s not but clear whether or not Meteor Lake will stay mobile-only or come to desktop like Ice Lake or Tiger Lake. However, there have been rumors for months a couple of potential Raptor Lake Refurbishment, so the latter sounds most unlikely. One alleged Intel document (opens in new tab) it solely confirms that Meteor Lake’s advertising and marketing identify is 14th Gen Core, but it surely would not fully dispel the rumors.
Meteor Lake ought to hit the retail market within the second half of this yr. After that, 7nm chips will face powerful competitors from AMD, together with Dragon Vary (Zen 4 + RDNA 2), Phoenix (Zen 4 + RDNA 3) and revamped Rembrandt-R and Barcelo-R chips.
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