TMSC’s 3nm Update: N3P and N3X on the Road with Density and Performance Gains
TSMC disclosure Vital roadmap updates for the N3 (3 nanometer class) household of course of applied sciences this week on the 2023 North American Expertise Symposium. The N3, TSMC’s final high-performance node primarily based on FinFET transistors, will final for a few years and can embody a number of variations, together with the N3P, a performance-enhancing optical discount from N3E, and the performance-oriented N3X for HPC purposes that tolerate excessive leakage and energy. .
Mass manufacturing on TSMC’s N3 (also referred to as N3B) course of expertise is already underway, however this node makes use of as much as 25 layers of maximum ultraviolet lithography and might even use EUV twin modelling, making it a very costly node to make use of. In consequence, TSMC expects nearly all of its prospects to make use of the N3E, which may use EUV as much as 19 layers, doesn’t use twin modeling EUV, has a wider processing window and higher throughput. The N3E, which will likely be used for high-volume manufacturing within the second half of 2023, may even kind the premise of TSMC’s subsequent evolution of 3nm.
Step one on this evolution will likely be N3P. This expertise will largely be optical miniaturization of the N3E which is able to embody 5% efficiency achieve on the similar leak, 5% to 10% energy discount on the similar hours, and another enhancements that present 4% increased transistor density. Hybrid chip consisting of fifty% logic, 30% SRAM and 20% analog circuits.
N3P, the N3E’s optical reducer, permits chip designers to reuse N3E IP within the new node, preserving the design guidelines. That is fairly vital as IP design corporations equivalent to Ansys, Cadence and Synopsys have already got numerous IPs focusing on N3E chips. In the meantime, optical shrinkage means density enhancements for every type of transistors and circuits, together with SRAM, a sort of circuit that has struggled with shrinkage in recent times (which is a foul factor, particularly for contemporary SRAM-intensive designs). The N3P will likely be prepared for mass manufacturing in 2024.
Following the N3P, TSMC plans to additional develop the N3 household and department out into high-performance computing purposes equivalent to CPUs and GPUs with the N3X. This manufacturing course of is envisioned to ship at the very least 5% increased frequencies in comparison with N3P whereas additionally permitting for considerably increased voltages, which is able to additional improve clocks on the expense of upper total leakage.
|Row 0 – Cell 0||N3X and N3P||N3P and N3E||N5 vs N3E||N3 and N5|
|Identical Energy Velocity Enchancment||+5% Fmax @ 1.2V||+5%||+18%||+10% ~ 15%|
|Identical Velocity Energy Discount||?||-5% ~ -10%||-32%||-25% ~ -30%|
|HVM Initialization||2025||H2 2024||Q2/Q3 2023||H2 2022|
TSMC claims that the N3X node can deal with at the very least 1.2 V, which is kind of a excessive voltage for a 3 nm class fabrication expertise. This comes with a big trade-off as TSMC expects a staggering 250% improve in energy leakage in comparison with the N3P. This highlights that the N3X is primarily appropriate for HPC CPUs, and that chip designers would require warning when creating power-hungry chips with the best efficiency, equivalent to knowledge heart CPUs and compute GPUs.
By way of transistor density, the N3X will match the capabilities of the N3P. TSMC didn’t specify whether or not the N3P and N3E would have harmonized design guidelines, leaving room for intrigue as as to whether designs may very well be moved between the 2 nodes.
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